1. Field of the Invention
The present invention relates to the shape of a printed pattern on a printed wiring board, and more particularly, to a printed wiring board for a high-speed circuit requiring adjustment of signal propagation times between respective electronic components.
2. Description of the Related Art
In printed wiring boards, the speed of integrated circuits (ICs) mounted thereon is increasing. Accordingly, in order to normally operate digital circuits operating with synchronizing signals, it is necessary to adjust signal transmission times in wiring patterns for propagating synchronizing signals, such as clock signals, from a clock-signal-generator IC to a memory IC. In wiring a bus which includes a plurality of wiring patterns, the signal transmission times between two ICs must be the same. Since skew is generated due to the difference between signal transmission times, it is desirable to minimize the difference.
FIG. 19 is a diagram illustrating a conventional technique. In FIG. 19, there is shown a printed circuit board 100. A clock-signal generator IC 102, and synchronous dynamic random access memory (SDRAM) ICs 103, 104 and 105 having the same electronic characteristics are mounted on a printed wiring board 101. In this circuit, synchronized clock signals A, B and C are transmitted from the clock-signal generator IC 102 to the SDRAM ICs 103, 104 and 105 via wiring patterns 110, 120 and 130, respectively. The distance from the clock-signal generator IC 102 to SDRAM ICs 103, 104 and 105 differs, because of mounting limitations. There are also shown IC leads 106, 107, 108 and 109.
In this high-speed circuit, it is desirable for the SDRAM ICs 103, 104 and 105 to operate simultaneously. Accordingly, the signal transmission times of the clock signals A, B and C from the clock-signal generator IC 102 to the SDRAM ICs 103, 104 and 105 must be the same. By forming a zigzag pattern 121 in wiring pattern 120, and forming a zigzag pattern 131 longer than the zigzag pattern 121 at the wiring pattern 130, the lengths of the wiring patterns 110, 120 and 130 are made the same, so that the signal transmission times of the clock signals A, B and C are the same.
FIG. 20 illustrates a technique relating to a bus wiring pattern between two ICs. In FIG. 20, there is shown a printed circuit board 200. A memory controller IC 202 and an SDRAM IC 203 are mounted on a printed wiring board 201. The memory controller IC 202 and the SDRAM IC 203 are interconnected by a bus wiring pattern, so that a bus signal is transmitted from the memory controller IC 202 to the SDRAM IC 203. In FIG. 20, in order to facilitate explanation, only three wiring patterns 210, 220 and 230 of the bus wiring pattern are shown, and other wiring patterns are omitted. It is necessary to adjust signal transmission times of the bus signal from the memory controller IC 202 to the SDRAM IC 203. In order to provide the same wire length for the wiring patterns 210, 220 and 230, a zigzag pattern 221 is formed at the wiring pattern 220, and a zigzag pattern 231 longer than the zigzag pattern 121 is formed at the wiring pattern 230. There are also shown IC leads 206 and 207.
FIG. 21 is a diagram illustrating another technique. In FIG. 21, there is shown a printed circuit board 300. A clock-signal generator IC 302, a memory controller IC 303 and an SDRAM IC 304 are mounted on a printed wiring board 301. The clock-signal generator IC 302 is mounted at a portion closer to the memory controller IC 303 than the SDRAM IC 304 because of mounting limitations. In this circuit, a clock signal D and a clock signal E are transmitted from the clock-signal generator IC 302 to the memory controller IC 303 and the SDRAM IC 304 via wiring patterns 310 and 320, respectively. The memory controller IC 303 and the SDRAM IC 304 are interconnected by a bus wiring pattern 330. During data writing into the SDRAM IC 304, the memory controller IC 303 transmits a bus signal F to the SDRAM IC 304 via the bus wiring pattern 330 using the clock signal D. During data reading from the SDRAM IC 304, the SDRAM IC 304 transmits a bus signal F′ to the memory controller IC 303 via the bus wiring pattern 330 using the clock signal E. There are also shown IC leads 306, 307 and 308.
In this high-speed circuit, it is desirable for the clock signal E and the bus signal F to simultaneously reach the SDRAM IC 304. It is also desirable for the clock signal D and the bus signal F′ transmitted from the SDRAM IC 304 to the memory controller IC 303 to reach the memory controller IC 303 simultaneously.
Accordingly, in such two-way transmission, if the input/output DC and AC characteristics of the clock-signal generator IC 302 and the SDRAM IC 304 are to be identical, the signal transmission time to the memory controller IC 303 must be the same for the clock signals D and E. If the input/output DC and AC characteristics of the clock-signal generator IC 302 and the SDRAM IC 304 differ, signal transmission times must be adjusted depending on the difference. Accordingly, the signal transmission time of the clock signal D is adjusted by forming a zigzag pattern 311 at the wiring pattern 310 for transmitting the clock signal D.
As still another technique, U.S. Pat. No. 5,777,526 discloses a method for adjusting, when there is a difference between propagation times of signals transmitted via two strip conductors, a propagation velocity per unit length by changing the dielectric constant of a dielectric disposed immediately below a strip conductor.
It has become clear that, in the zigzag pattern approach, there is not necessarily a perfect correlation between wire length and propagation time (Electronics Jisso Gakkaishi, Vol. 4, No. 7 (2001), p 549, p 565). Accordingly, it is impossible to adjust the propagation times of clock signals only by adjusting the wire length using a zigzag pattern.
Another problem is in that, in order to form a zigzag pattern, a region for the zigzag pattern must be secured when designing a printed wiring board, resulting in limitation in the degree of freedom of design. Specifically, in the case of the bus wiring pattern shown in FIG. 20, since wires are densely packed, it may be impossible to implement a zigzag pattern because of limitation of a space.
In the method described in U.S. Pat. No. 5,777,526, although the propagation times of signals can be adjusted, formation of substances having different dielectric constants within the same substrate is unrealistic, because complicated manufacturing processes must be used, and therefore the production cost will be greatly increased. For example, in a digital circuit including a high-speed memory and a central processing unit (CPU), since the number of signal patterns is large and signal patterns must be narrow pitch, it is very difficult and unrealistic to change dielectric constants for respective patterns.